Hallo, Luke Iannini (pd) hat gesagt: // Luke Iannini (pd) wrote:
I am aware of the stack overflow possibility, and I'll probably block out routings that would cause that.
The intent is for the input to reach all outputs before any new input is processed (i.e. before any new input changes the routing configuration of the spigots). I see my mistake more clearly now, but the solution has not reached me yet. I could buffer the inputs with [f] or [fifo]s, but that seems like it will become untenable; I'll keep trying.
Hm, I'm still not clear about how the routing should look like. Maybe you can give a kind of more formal specification: Assuming you have a (m,n)-matrix with m rows and n columns. With m=4 and n=3 this will be printed through mtx_print as:
matrix: 0 0 0 0 0 0 0 0 0 0 0 0
A signal~ matrix [mtx_*~] will have m=4 outputs and n=3 inputs then, that could be selected with the above message matrix. Setting element (i,j) to 1 will open outlet~ i for inlet~ j then.
Back to the message patchbay: How should this behave, if you set element (i, j) to 1? Using the signal analogy I would assume, that all messages "sent to inlet j" (that is, [list prepend]'ed with j) should be "sent to outlet i" (that is: the first element of the new list, which was j, will be set to i so that you can [route] it), but from your patch it seems you want to achieve something different?
Anyways I attached a message-patchbay which works like I proposed to illustrate what I mean.
Ciao
Frank Barknecht _ ______footils.org_ __goto10.org__