On Fri, 2006-08-11 at 11:11 +0200, Enrique Erne wrote:
it'd be nice to have a setable r~/s~ or catch~/throw~... attached a solution with throw~ -> catch~ -> s~ -> r~ so you can set both. that will delay the signal about 2 blocks :-(
it will in the worst case, but in the best case there won't be any delay. this depends on creation order.
if you create: catch~ - throw~ and r~ - s~, you'll have a delay of two blocks.
if you create them in this order: throw~ - catch~ and s~ - r~, there is no delay at all.
if a certain pair causes a delay is dependent on where its objects are in the dsp-chain. of course a [r~] cannot read what its related [s~] not already has been written into the buffer, so it reads the buffer from the last cycle.
since the execution is considered not be defined, when someone connects an outlet with two inlets (which actually *is* defined, but you cannot see it), there should be also way of telling pd, in which order a [send~] should write and its [r~] should read. having to care about their creation order is kind of a hackish programming style.
roman
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